Next-gen CPUs & L2

[CmdrFly]

I notice Intel has been using shared cache in multi-core processors, while AMD has cache banks dedicated to each processor.

I can guess at the foreseeable pros & cons with each, but does anyone know what the real-world benefits and penalties are of shared vs. dedicated L2?

 

[exodusamphi]

Shared allow more use for single core needs, whereas dedicated is ok for decent multithreading apps... but if you have same single and same dedicated for multithreading id guess it would be the same.

 

[Tagrineth]

For a segregated cache you will probably get slightly more consistent performance due to having two independent pathways, with each core being guaranteed its own route.

The catch, though, is that when doing a single-threaded task or tasks, and even for multi-threading to an extent, you're going to have replicated data, because each core can't access the other's cache.

Shared cache avoids the replication problem and can increase performance under heavier loads by having more "effective" memory available.

 

[CmdrFly]

The catch, though, is that when doing a single-threaded task or tasks, and even for multi-threading to an extent, you're going to have replicated data, because each core can't access the other's cache.

Shared cache avoids the replication problem and can increase performance under heavier loads by having more "effective" memory available.

If there's duplicate data in each core's independent cache, wouldn't that mean that the cores are crunching the same instruction and thus being used incorrectly?

 

[Anttaru]

Shared leans towards the traditional way of hyperthreading, except it's in a single unit, rather than dual chipset with 2 processors. This one wants to do things faster, as opposed to do more at once, which isn't a bad idea at all.

I can't say i've personally tested the difference. But i would imagine the multiprocessor with shared cache would tackle a single task much quicker than the multiprocessor that does not share cache with it's seperate cells, and also handle very well when running multiple tasks, in the traditional sense.

The multi processor that does not share cache with the seprate cells. I'll read more about that, cause i'm having this theory it will hold back on feeding information into the RAM, then when it does, it will be a rather large step in the direction of freezing the machine. Then again that can be solved with more memory.

Ninja Edit: If the seprate cores actually dumped completed tasks in the ram at the same time that is. Question is, how many mp3's or videos would it take to make the multiprocessors start to lag out as opposed to it's rival.

 

[Tagrineth]

If there's duplicate data in each core's independent cache, wouldn't that mean that the cores are crunching the same instruction and thus being used incorrectly?

Not necessarily; if they're doing two threads in the same app their data might cross over, especially in an application made with a hyperthreading mentality rather than outright multithreading.

 

[CmdrFly]

Not necessarily; if they're doing two threads in the same app their data might cross over, especially in an application made with a hyperthreading mentality rather than outright multithreading.

The same situation could exist with single-cache multi-core processors then, can it not?

Unless they have (in single-cache situation) a program/algorithm constantly running that compares everything one core dumps to L2 to what another core dumps to the same bank. But such a process/algorithm seems like a waste of cycles, particularly since you'd think it would have to reside in L2 itself to be able to run compares fast enough (thus costing cycles and L2 storage).

 

[Tagrineth]

The same situation could exist with single-cache multi-core processors then, can it not?

Unless they have (in single-cache situation) a program/algorithm constantly running that compares everything one core dumps to L2 to what another core dumps to the same bank. But such a process/algorithm seems like a waste of cycles, particularly since you'd think it would have to reside in L2 itself to be able to run compares fast enough (thus costing cycles and L2 storage).

That by and large depends on the application programmer, I would think.

 

[CmdrFly]

Barcelona, the 65nm quad-core next-generation Opteron from AMD, is expected to launch this summer with 2MB of L3 cache. L3 cache on the K8L architecture is shared over all four cores, yet each core has an independent L2 cache as well. More details on how this new cache operation works was detailed in June 2006 on DailyTech.

http://www.dailytech.com/AMDs+45nm+Opterons+Scheduled+for+2008/article5984.htm

So AMD has both independent L2, and common L3. I thought I remember reading that Intel uses L3 but I could very well be mistaken. Can anyone confirm? Not seeing any answers in my brief search.